The ideal candidate will have following skills and background:
Could either be a recent graduate with relevant project experience and some hands on VHDL/Verilog experience, or have one or two years experience in an ASIC/FPGA verification domain. An excellent academic background with University degree in Electronics / Computer Science (or related field) is also required.
Basic knowledge of SystemVerilog/OVM/UVM and/or “e” (Specman) languages are essential, as are excellent communication skills and a real passion for System on Chip verification.
Knowledge of Hardware Description Languages (VHDL/Verilog)
Proficient Unix user
Fluent English is a must
Following skills will be a plus:
Experience of Verilog, VHDL and scripting languages
Familiar with scripting tools and languages (e.g. bash, csh, awk, Perl)
Familiar with development tools (e.g. make and versioning tools (e.g. SVN/CVS)
Develop or maintain ASIC verification environments to support ASIC development
Development of SystemVerilog/UVM VIP, constrained random verification environment, test plans and regressions
Execution of block or system level verification
Working with design team in all the phases of the verification process to meet quality requirements at block and system level
Proactively collaborate with team members in different locations
You will be given both formal and on the job training to be successful.
This is a full time contractand as a top company in a fast growing industry, we have a great working environment where engineering is our top priority. We manage to keep a vibrant, startup-like environment where innovation and technology advancement occur on a daily basis. You will have the chance to shine as a top contributor and rise in the ranks of a growing company while working in an exciting, technology space.
Apply by sending your CV via klikdoposla